1. Field of the Invention
The present invention relates to a reference potential generating circuit for use in a liquid crystal display apparatus.
2. Description of the Related Art
FIG. 8 is a schematic diagram showing a prior art liquid crystal display apparatus.
In LCD panel 2, a matrix of liquid crystal pixels including pixel 2a are formed. LCD panel 2 holds a liquid crystal layer between a TFT substrate and an opposite substrate. On the TFT substrate, data lines, scanning lines perpendicular to data lines, a matrix of TFT (thin-film transistor) and a matrix of display electrodes are formed. On the opposite substrate, common opposite electrode is formed.
Common potential VC is applied from common voltage dividing circuit 3 to the opposite electrode of liquid crystal pixel 2a, and display electrode of liquid crystal pixel 2a is connected through TFT 2b to data line DLj. A gate of TFT 2b is connected to scanning line SLi. A scanning pulse of, for example, a high being 20V and a low being -5V are applied from scanning driver 4 to the scanning lines SLi. With this pulse, TFT 2b is turned on to cause a signal potential from data driver 5 to be applied through data line DLj and TFT 2b onto the display electrode of liquid crystal pixel 2a. The signal potential is one of reference potentials V0 through V9 provided from reference potential generating circuit 6 to data driver 5 or one of further divided potentials of reference potentials V0 through V9, and the same is determined in compliance with display data DAT. Scanning driver 4 and data driver 5 are controlled by control signals from control circuit 7, and the control signals are generated based on horizontal synchronization signals *HS and vertical synchronization signals *VS.
The display electrode potential of liquid crystal pixels 2a is lowered by .DELTA.Vgsd according to the parasitic capacity between the gate and source of TFT 2b and between the source and the rain thereof when the scanning pulse falls down to a low to turn off TFT 2b.
It is assumed that one of V0 through V9 is applied to data line DLj according to display data DAT. In a case where V0 through V9 are, for example, reference potential set V_SET1 (V10 through V19) shown in FIG. 10, the display electrode potential of liquid crystal pixel 2a becomes as in reference potential set V_SET2 (V20 through V29) by shifting down of .DELTA.Vgsd. Liquid crystal is driven by alternate current, so the polarity of application voltage is reversed with respect to the common potential VC, for example, at every frame. In a case where the display data is constant, for example, voltages (V21-VC) and -(VC-V28) are alternately applied to liquid crystal pixels 2a at every frame. Since (V21-VC)&lt;(VC-V28), the image flickers. Furthermore, the time average of accumulation charge of liquid crystal pixel 2a does not become zero, charge is accumulated in liquid crystal pixel 2a to cause an image to be residual.
Hence, if it is constructed that, taking .DELTA.Vgsd into consideration, the potentials of V0 through V9 are raised as reference potential set V_(V30 through V39) so as to secure reference potential set V_SET1(V10 through V19) after shifting down by .DELTA.Vgsd, the above-mentioned problem can be solved.
That is, the center potential of a pair of reference potentials (V0+V9)/2, (V1+V8)/2, (V2+V7)/2, (V3+V6)/2, and (V4+V5)/2, should be set to VC+.DELTA.Vgsd. .DELTA.Vgsd=.DELTA.V-.mu.(Vu-Vd)/2 holds, wherein Vd denotes V9, V8, V7, V6 or V5, while Vu denotes V0, V1, V2, V3 or V4, respectively, and wherein .DELTA.V and .mu. are positive and determined by the capacity of liquid crystal pixel 2a, the parasitic capacity of TFT 2b and so on.
Therefore, the reference potential generating circuit may be constituted so that the following equation holds. EQU (Vu+Vd)/2=VC+.DELTA.V-.mu.(Vu-Vd)/2 (1)
FIG. 9 shows a prior art reference potential generating circuit.
In FIG. 9, R11 through R21 and R25 through R27 are fixed resistors for voltage dividing, R28 and R29 are fixed resistors for compensating .DELTA.Vgsd, and 11, 12, 21, 22, 31 through 33 and 46 through 48 are voltage follower circuits for voltage buffering with an amplification factor of 1.
V0 and V9 are determined by outside reference potential generating circuit 10A, V4 and V5 are mainly determined by inside reference potential generating circuit 20A, voltage between V0 and V4 is divided by voltage dividing circuit 30 to cause V1 through V3 to be picked up, and voltage between V5 and V9 is divided by voltage dividing circuit 40 to cause V6 through V8 to be picked up. The resistance values of resistors R11 and R21 are equal to each other, the resistance values of resistors R26 and R27 are equal to each other, and the resistance values of resistors R12 through R15 are equal to the resistance values of resistors R20 through R17, respectively.
In the case where resistors R28 and R29 are not connected, the upper potentials V0 to V4 and lower potentials V9 to V5 become symmetrical with respect to the common voltage VC as reference potential set V_of FIG. 10. By resistor R28, or resistors R28 and R29 as in FIG. 9 of a proper resistance value for compensating .DELTA.Vgsd, it is possible to meet equation (1).
On the other hand, since the liquid crystal transmittance of LCD panel 2 changes according to the visual angle of a viewer who looks thereat, it is necessary to make the reference potential adjustable by employing a variable resistor instead of fixed resister 25. Furthermore, it is necessary to employ a variable resistor instead of fixed resistor 25 in order to perform .gamma.-correction.
However, in the case of construction of FIG. 9, although the above-mentioned equation (1) can hold with respect to a certain resistance value of resistor 25, the equation (1) is not satisfied if the resistance value is changed, thereby the above-mentioned flickering or residual image occurs.